6.17 System Interface Request and Response Protocol
Processor coherency state responses are issued by the processor in the same order that the corresponding external coherency requests are received. Processor coherency state and data responses may occur in adjacent SysClk cycles.
The processor issues a processor coherency state response by driving the secondary cache block tag quality indication on SysState[2], driving the secondary cache block former state on SysState[1:0], and asserting SysStateVal* for one SysClk cycle. The processor coherency state responses are issued in an order designated by the external coherency requests and will always be issued before an associated processor coherency data response. Note that processor coherency state responses can be pipelined ahead of the associated processor coherency data responses, and processor coherency data responses can be returned out-of-order. These cases typically arise from external coherency requests hitting outgoing buffer entries. (See page 126 of Errata.) Figure 6-24 depicts two external coherency requests and the resulting processor coherency state responses.
Figure 6-24 Processor Coherency State Response Protocol
The processor issues a processor coherency data response with a single empty cycle followed by either 8 or 16 data cycles. The empty cycle consists of negating SysVal* for a single SysClk cycle. The data cycles consist of the following:
The processor may only issue a processor coherency data response when the System interface is in master state and SysWrRdy* was asserted two SysClk cycles previously. Note that the empty cycle is considered the issue cycle for a processor coherency data response. If the System interface is not already in master state, the processor must first assert SysReq*, and then wait for the external agent to relinquish mastership of the System interface bus by asserting SysGnt* and SysRel*. If the System interface is already in master state, the processor may issue a processor coherency data response immediately.
When SysStateVal* is negated, SysState[0] provides the processor coherency data response indication. The processor asserts the processor coherency data response indication when there are one or more processor coherency data responses pending issue in the outgoing buffer. Once asserted, the indication is negated when the first doubleword of the last pending issue processor coherency data response is issued to the system interface bus. The processor coherency data response indication is not affected by SysWrRdy*. However, as previously noted the processor may only issue a processor coherency data response when SysWrRdy* was asserted two SysClk cycles previously.Figure 6-25 depicts one external coherency request and the resulting processor coherency state and data responses.
Figure 6-25 Processor Coherency Data Response Protocol
